1. Field of the Invention
This invention is related to the field of timing methodologies for integrated circuit development and, more particularly, to measuring IR drop on power supply interconnect.
2. Description of the Related Art
The design of an integrated circuit, from concept to “tape out” (i.e. the transmission of the data describing the integrated circuit to the fabrication foundry), is a complex series of parallel, interdependent processes such as logic design, circuit design, synthesis, timing analysis, place and route, verification, etc. To successfully fabricate an integrated circuit that performs as specified, all of the various processes must be completed as accurately as possible.
Many integrated circuit design methodologies rely on synthesis using “standard cell” circuits for significant portions of the design. A standard cell may be a predesigned circuit (including layout and interconnection of the transistors used to form the circuit). The standard cell may be instantiated in the integrated circuit and connected to other instantiations of standard cells to implement a block described in a hardware design language (HDL). The same standard cell may be instantiated as many times as desired to realize various functionality in the blocks that form an integrated circuit. Standard cells may be more briefly referred to herein as “cells.” Typically, a library of standard cells are designed and provided for synthesis. The library can include a variety of logic gates and somewhat more complex functions that are expected to occur frequently in the design. Multiple cells may be defined for a given function, with each cell having a different drive strength. The multiple cells provide the ability to trade off size for speed in the synthesis step.
One of the challenges with standard cells is the correct determination of delay in the cells under various operating conditions. The delays are used for timing analysis, and thus must be as accurate as possible (and conservative where accuracy might be questionable). For example, a maximum delay parameter for a standard cell must be at least as large as the actual delay of the corresponding circuitry after fabrication (or larger). If the maximum delay parameter were shorter than the actual delay, the block would appear to meet timing during the design but would fail to operate properly when fabricated.
One of the factors that affect the timing of standard cells is the amount of voltage drop on power and ground connections in the cell. The voltage drop is the result of resistance in power/ground network and the combined current of all transistors in the cell drawing current on the grid at any particular time. Accordingly, the drop is often referred to as the IR drop (current (I) multiplied by resistance (R)). To ensure IR drop is within the allocated IR budget for timing analysis, industry standard IR analysis tools are often used. For standard cells, static peak IR flow is used. Static peak IR flow assumes the worst case scenario of all transistors in the entire cell being turned on at the same time. This approach is too pessimistic in many cells. For example, in complex or multiple stage cells, static peak IR flow is overly pessimistic because timing differences between stages are not taken into account. In another example, if transistors within the cell are separated by inverting logic, the transistors and nets separated by inverting stages are mutually exclusive.